W25Q80BLSVIG TR

W25Q80BL 2.5V 8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI -1- Publication Release Date: April 07,2014 Revision G1 W25Q80BL Table of Contents 1. GENERAL DESCRIPTION ............................................................................................................... 5 2. FEATURES ....................................................................................................................................... 5 3. PACKAGE TYPES ............................................................................................................................ 6 3.1 Pin Configuration SOIC 150 / 208-mil, VSOP 150-mil.......................................................... 6 3.2 PAD Configuration WSON 6x5-mm, USON 2X3-MM .......................................................... 6 3.3 Pin Description SOIC, VSOP, WSON, USON ...................................................................... 7 3.4 Pin Descriptions .................................................................................................................... 8 3.5 3.4.1 Chip Select (/CS) ................................................................................................................... 8 3.4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ....................................... 8 3.4.3 Write Protect (/WP) ................................................................................................................ 8 3.4.4 HOLD (/HOLD) ....................................................................................................................... 8 Serial Clock (CLK) ................................................................................................................ 8 4. BLOCK DIAGRAM ............................................................................................................................ 9 5. FUNCTIONAL DESCRIPTION ....................................................................................................... 10 5.1 5.2 SPI OPERATIONS ............................................................................................................. 10 5.1.1 Standard SPI Instructions .................................................................................................... 10 5.1.2 Dual SPI Instructions ............................................................................................................ 10 5.1.3 Quad SPI Instructions .......................................................................................................... 10 5.1.4 Hold Function ....................................................................................................................... 10 WRITE PROTECTION ....................................................................................................... 11 5.2.1 6. Write Protect Features ......................................................................................................... 11 CONTROL AND STATUS REGISTERS......................................................................................... 12 6.1 6.2 STATUS REGISTER .......................................................................................................... 12 6.1.1 BUSY.................................................................................................................................... 12 6.1.2 Write Enable Latch (WEL) ................................................................................................... 12 6.1.3 Block Protect Bits (BP2, BP1, BP0) ..................................................................................... 12 6.1.4 Top/Bottom Block Protect (TB)............................................................................................. 12 6.1.5 Sector/Block Protect (SEC) .................................................................................................. 12 6.1.6 Complement Protect (CMP) ................................................................................................. 13 6.1.7 Status Register Protect (SRP1, SRP0) ................................................................................ 13 6.1.8 Erase/Program Suspend Status (SUS) ................................................................................ 13 6.1.9 Security Register Lock Bits (LB3, LB2, LB1) ........................................................................ 13 6.1.10 Quad Enable (QE) .............................................................................................................. 14 6.1.11 Status Register Memory Protection (CMP = 0) .................................................................. 15 6.1.12 Status Register Memory Protection (CMP = 1) .................................................................. 16 INSTRUCTIONS................................................................................................................. 17 6.2.1 Manufacturer and Device Identification ................................................................................ 17 6.2.2 Instruction Set Table 1 (Erase, Program Instructions) -2- (1) ...................................................... 18 W25Q80BL 7. 6.2.3 Instruction Set Table 2 (Read Instructions) .......................................................................... 19 6.2.4 Instruction Set Table 3 (ID, Security Instructions) ................................................................ 20 6.2.5 Write Enable (06h) ............................................................................................................... 21 6.2.6 Write Enable for Volatile Status Register (50h) ................................................................... 21 6.2.7 Write Disable (04h) .............................................................................................................. 22 6.2.8 Read Status Register-1 (05h) and Read Status Register-2 (35h) ........................................ 23 6.2.9 Write Status Register (01h) .................................................................................................. 23 6.2.10 Read Data (03h) ................................................................................................................. 25 6.2.11 Fast Read (0Bh) ................................................................................................................. 26 6.2.12 Fast Read Dual Output (3Bh) ............................................................................................. 27 6.2.13 Fast Read Quad Output (6Bh) ........................................................................................... 28 6.2.14 Fast Read Dual I/O (BBh) .................................................................................................. 29 6.2.15 Fast Read Quad I/O (EBh) ................................................................................................. 31 6.2.16 Word Read Quad I/O (E7h)................................................................................................ 33 6.2.17 Octal Word Read Quad I/O (E3h) ...................................................................................... 35 6.2.18 Set Burst with Wrap (77h) .................................................................................................. 37 6.2.19 Continuous Read Mode Bits (M7-0) ................................................................................... 38 6.2.20 Continuous Read Mode Reset (FFh or FFFFh) ................................................................. 38 6.2.21 Page Program (02h) ........................................................................................................... 39 6.2.22 Quad Input Page Program (32h) ........................................................................................ 40 6.2.23 Sector Erase (20h) ............................................................................................................. 41 6.2.24 32KB Block Erase (52h) ..................................................................................................... 42 6.2.25 64KB Block Erase (D8h) .................................................................................................... 43 6.2.26 Chip Erase (C7h / 60h) ...................................................................................................... 44 6.2.27 Erase / Program Suspend (75h) ........................................................................................ 45 6.2.28 Erase / Program Resume (7Ah) ......................................................................................... 46 6.2.29 Power-down (B9h) .............................................................................................................. 47 6.2.30 Release Power-down / Device ID (ABh)............................................................................. 48 6.2.31 Read Manufacturer / Device ID (90h) ................................................................................. 50 6.2.32 Read Manufacturer / Device ID Dual I/O (92h) .................................................................. 51 6.2.33 Read Manufacturer / Device ID Quad I/O (94h) ................................................................. 52 6.2.34 Read Unique ID Number (4Bh) .......................................................................................... 53 6.2.35 Read JEDEC ID (9Fh) ........................................................................................................ 54 6.2.36 Read SFDP Register (5Ah) ................................................................................................ 55 6.2.37 Erase Security Registers (44h) .......................................................................................... 56 6.2.38 Program Security Registers (42h) ...................................................................................... 57 6.2.39 Read Security Registers (48h) ........................................................................................... 58 (1) ELECTRICAL CHARACTERISTICS ............................................................................................ 59 7.1 Absolute Maximum Ratings(1)(2) ....................................................................................... 59 7.2 7.3 Operating Ranges............................................................................................................... 59 Power-Up Power-Down Timing and Requirements(1) ....................................................... 60 -3- Publication Release Date: April 07,20143 Preliminary - Revision G1 W25Q80BL 7.4 8. 9. 7.5 DC Electrical Characteristics .............................................................................................. 61 AC Measurement Conditions(1) ......................................................................................... 62 7.6 AC Electrical Characteristics .............................................................................................. 63 7.7 AC Electrical Characteristics (cont’d) ................................................................................. 64 7.8 Serial Output Timing ........................................................................................................... 65 7.9 Serial Input Timing .............................................................................................................. 65 7.10 Hold Timing ........................................................................................................................ 65 PACKAGE SPECIFICATION .......................................................................................................... 66 8.1 8-Pin SOIC 150-mil (Package Code SN)............................................................................ 66 8.2 8-Pin VSOP 150-mil (Package Code SV) ........................................................................... 67 8.3 8-Pin SOIC 208-mil (Package Code SS) ............................................................................ 68 8.4 8-Pad WSON 6x5mm (Package Code ZP) ........................................................................ 69 8.5 8-Pad USON 2x3-mm (Package Code UX) ....................................................................... 71 ORDERING INFORMATION .......................................................................................................... 72 9.1 10. Valid Part Numbers and Top Side Marking ........................................................................ 73 REVISION HISTORY ...................................................................................................................... 74 -4- W25Q80BL 1. GENERAL DESCRIPTION The W25Q80BL (8M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.3V to 3.6V power supply with current consumption as low as 4mA active and 1µA for power-down. The W25Q80BL array is organized into 4,096 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q80BL has 256 erasable sectors and 16 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See figure 2.) The W25Q80BL supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 50MHz are supported allowing equivalent clock rates of 100MHz (50MHz x 2) for Dual I/O and 200MHz (50MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation. A Hold pin, Write Protect pin and programmable write protection, with top, bottom or complement array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification with a 64-bit Unique Serial Number. 2. FEATURES  Family of SpiFlash Memories – W25Q80BL: 8M-bit/1M-byte (1,048,576) – 256-byte per programmable page – Standard SPI: CLK, /CS, DI, DO, /WP, /Hold – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 – 4mA active current,